The performance of silicon carbide (SiC) power metal-oxide-semiconductor field effect transistor (MOSFETs) can be impacted, as compared with theoretical performance parameters of such devices, due, at least in part, to imperfections of a MOS interface, such as an interface between SiC material and gate a dielectric (e.g., gate oxide), of a MOSFET implemented in SiC. While inversion-layer mobility for lateral crystal faces in SiC devices does not significantly affect performance for a SiC MOSFET (e.g., lateral MOSFET) having a low (e.g., 5 volts) threshold voltage (Vt), devices with such Vt values do not meet the performance and reliability requirements of many power MOSFET application (e.g., operating voltages of 100 V or greater). For example, at such operating voltages, a low Vt device may be normally on, e.g., regardless of applied gate voltage.
However, merely increasing the Vt of such devices may not allow for achieving desired performance parameters due, at least in part, to the fact that inversion-layer mobility in SiC (e.g., in lateral SiC crystal faces) rapidly decreases with increasing Vt, leading to a number of difficult tradeoff decisions when designing SiC power MOSFETs. Such decreases in carrier mobility due to increases in Vt may be due, at least in part, to scattering mobile charge carriers at areas of trapped interface charge.
Vertical SiC crystal faces (e.g., crystal faces 11-20) tend to have better tradeoffs between mobility and Vt. Accordingly, trench gate MOSFETs can benefit from this better Vt tradeoff (e.g., due to having a vertical channel). Unfortunately, trench gate MOSFETs can be difficult to implement in SiC due to other reliability concerns. For instance, electric fields in SiC MOSFETs are on the order of ten times higher than in similar devices in silicon (Si) substrates. These increased electric fields can cause reliability issues in SiC trench gate MOSFETs, such as susceptibility to voltage breakdown damage at the corners of the trench gate (e.g., due to electric field crowding).